Senior Design Verification Engineer — SoC/IP Mastery

A leading technology company is seeking a hardworking design verification engineer in Beaverton, OR. You will ensure bug-free first silicon for SoC/IP and will develop verification environments. Candidates should have a BS degree in a technical field and at least 3 years of relevant experience. The role involves using SystemVerilog/UVM, and knowledge of LLMs is advantageous. Join us and contribute to innovative product development. #J-18808-Ljbffr