Design Verification Engineer — SoC/IP (SystemVerilog/UVM)

A leading technology company seeks a hardworking design verification engineer in San Francisco. This role includes developing test plans and methodologies to ensure bug-free silicon for cutting-edge products. Candidates should have a BS degree with at least 3 years of experience, strong knowledge in SystemVerilog and UVM, and a passion for innovation. A competitive salary package is offered, along with stock options, comprehensive benefits, and opportunities for career advancement. #J-18808-Ljbffr