DRAM Design Validation Engineer – SoC Memory

A leading technology company in Cupertino, California is seeking a DRAM Design Validation Engineer to ensure successful integration of DRAM memories with SoC devices. You will work with design and verification engineers, collaborate with vendors, and drive roadmaps for memory technologies. This role demands a background in DRAM development and excellent teamwork skills. Competitive compensation packages include base salary, stock options, and comprehensive benefits. #J-18808-Ljbffr