Senior IP Verification Engineer - High-Speed Protocols

A leading tech company in San Jose is seeking a Senior Design Verification Engineer to lead the verification and validation of next-generation IPs. The role involves developing verification plans, writing test cases, and collaborating with cross-functional teams. Candidates must have over 9 years of experience with Verilog, System Verilog, and protocol verification expertise. The salary range is $142.6k - $206.5k USD. #J-18808-Ljbffr