FPGA Design Verification Engineer: RTL, UVM, SystemVerilog

A technology firm is seeking a skilled FPGA Design Verification Engineer in Menlo Park, California. Responsibilities include designing verification tests, analyzing results, and collaborating with engineers to resolve issues. The ideal candidate has expertise in ASIC or FPGA RTL design, system Verilog, and scripting languages like TCL and Python. A degree in Computer Science or Electrical Engineering is preferred, or equivalent experience. #J-18808-Ljbffr