Qualcomm
ASIC Methodology Engineer – Qualcomm
Company : Qualcomm Technologies, Inc.
Job Area : Engineering Group > ASICS Engineering (Global SOC organization)
General Summary : The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development.
About the Role : As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state‑of‑the‑art design analytics platform, with consequential impact on the power, performance, area, and quality of Qualcomm’s products.
Required For This Role
M.S./Ph.D. degree in Electrical Engineering or Computer Science with 1‑2 years of relevant experience with ASIC/VLSI design tools and flows.
Strong programming skills in Python.
Hands‑on experience with static timing analysis (STA) tools, e.g., PrimeTime and Tempus.
Problem‑solving and analytical mindset.
Preferred Qualifications
Critical thinking with good software architecture understanding to develop platforms at scale.
Familiarity with GenAI models (e.g., LLMs such as GPT, Llama, etc.) and their application in real‑world solutions, such as chatbots.
Experience designing and developing agentic AI systems.
Experience with version control tools like Perforce or Git.
Experience with place & route tools and a good understanding of the ASIC RTL‑GDSII design flow.
Where you will be working This role requires the candidate to be onsite in San Diego or Santa Clara, CA.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR Ph.D. in Science, Engineering, or related field.
Equal Opportunity Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Please e‑mail disability‑accommodations@qualcomm.com or call your local Qualcomm office for accommodations.
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay Range and Benefits Salary: $115,600.00 – $173,400.00 (location specific). In addition to base salary, Qualcomm offers a competitive annual discretionary bonus program, the opportunity for annual RSU grants, and a highly competitive benefits package. For more details, visit Qualcomm's US benefits page.
How to Apply For more information about this role, please contact Qualcomm Careers.
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Job Area : Engineering Group > ASICS Engineering (Global SOC organization)
General Summary : The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development.
About the Role : As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state‑of‑the‑art design analytics platform, with consequential impact on the power, performance, area, and quality of Qualcomm’s products.
Required For This Role
M.S./Ph.D. degree in Electrical Engineering or Computer Science with 1‑2 years of relevant experience with ASIC/VLSI design tools and flows.
Strong programming skills in Python.
Hands‑on experience with static timing analysis (STA) tools, e.g., PrimeTime and Tempus.
Problem‑solving and analytical mindset.
Preferred Qualifications
Critical thinking with good software architecture understanding to develop platforms at scale.
Familiarity with GenAI models (e.g., LLMs such as GPT, Llama, etc.) and their application in real‑world solutions, such as chatbots.
Experience designing and developing agentic AI systems.
Experience with version control tools like Perforce or Git.
Experience with place & route tools and a good understanding of the ASIC RTL‑GDSII design flow.
Where you will be working This role requires the candidate to be onsite in San Diego or Santa Clara, CA.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR Ph.D. in Science, Engineering, or related field.
Equal Opportunity Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Please e‑mail disability‑accommodations@qualcomm.com or call your local Qualcomm office for accommodations.
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay Range and Benefits Salary: $115,600.00 – $173,400.00 (location specific). In addition to base salary, Qualcomm offers a competitive annual discretionary bonus program, the opportunity for annual RSU grants, and a highly competitive benefits package. For more details, visit Qualcomm's US benefits page.
How to Apply For more information about this role, please contact Qualcomm Careers.
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