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Talently

Senior ASIC Design Engineer - AI Hardware & HPC

Talently, San Jose, California, United States, 95199

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A leading technology innovator is seeking a Senior ASIC Design Engineer to join their team in San Jose, California. In this role, you will design high performance compute and high-speed data transport logic specifically for AI inference workloads, collaborate with verification engineers, and integrate third-party IP into chiplet architectures. The ideal candidate will have over 5 years of experience in ASIC design, proficiency in SystemVerilog, and strong scripting skills in Python, Perl, or TCL. This is a full-time position offering competitive benefits, including medical and vision insurance, and a 401(k). #J-18808-Ljbffr