Talently
Senior ASIC Design Engineer
Location:
On Site - San Jose, California, United States
Base pay range:
$200,000.00/yr - $230,000.00/yr
Skills:
ASIC Design, SystemVerilog, High Performance Compute, High-Speed Data Transport, PCIe/HBM
About the Technology Company / The Opportunity Join a rapidly growing technology innovator dedicated to building next-generation infrastructure for AI advancement. This opportunity places you at the forefront of semiconductor and AI system design, empowering smarter devices and more sustainable data centers. As part of a world-class engineering team, you will contribute to the development of silicon solutions powering AI models, impacting the future of AI hardware and applications on a global scale.
Responsibilities
Design high performance compute and high-speed data transport logic optimized for AI inference workloads.
Integrate third-party and open source IP into complex chiplet architectures.
Collaborate with verification engineers to develop verification strategies, drive coverage closure, and debug cross-functional design issues.
Develop automation and methodologies to elevate productivity and product quality throughout the design process.
Create comprehensive technical documentation, including microarchitecture specifications and integration guides.
Contribute to architectural decisions that balance performance, power consumption, area, and development schedules.
Work closely with physical design teams to ensure RTL supports timing closure, power targets, and manufacturability on advanced process nodes.
Must-Have Skills
BS/MS in Electrical Engineering, Computer Engineering, or related field.
5+ years of hands‑on ASIC design experience with complex digital logic, particularly using SystemVerilog.
Demonstrated experience designing high performance compute and high-speed data transport logic.
Experience with fabric and high-speed IO integration (e.g., PCIe, HBM).
Proficiency with testbench creation, simulation environments, and synthesis flows.
Strong scripting abilities with Python, Perl, or TCL for design automation.
Self‑motivated with a track record of thriving in dynamic, start‑up environments.
Nice-to-Have Skills
Direct experience integrating open source IP for chiplet architectures.
Background in AI inference or building silicon solutions for AI/ML applications.
Experience developing automation around performance, power, and area trade‑offs.
Expertise in technical documentation, specification writing, and design reviews.
Familiarity with advanced process nodes and optimization for manufacturability.
Prior exposure to collaborative start‑up environments and multidisciplinary engineering teams.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Design
Industries Technology, Information and Media and Semiconductor Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
Referrals increase your chances of interviewing at Talently by 2x
#J-18808-Ljbffr
On Site - San Jose, California, United States
Base pay range:
$200,000.00/yr - $230,000.00/yr
Skills:
ASIC Design, SystemVerilog, High Performance Compute, High-Speed Data Transport, PCIe/HBM
About the Technology Company / The Opportunity Join a rapidly growing technology innovator dedicated to building next-generation infrastructure for AI advancement. This opportunity places you at the forefront of semiconductor and AI system design, empowering smarter devices and more sustainable data centers. As part of a world-class engineering team, you will contribute to the development of silicon solutions powering AI models, impacting the future of AI hardware and applications on a global scale.
Responsibilities
Design high performance compute and high-speed data transport logic optimized for AI inference workloads.
Integrate third-party and open source IP into complex chiplet architectures.
Collaborate with verification engineers to develop verification strategies, drive coverage closure, and debug cross-functional design issues.
Develop automation and methodologies to elevate productivity and product quality throughout the design process.
Create comprehensive technical documentation, including microarchitecture specifications and integration guides.
Contribute to architectural decisions that balance performance, power consumption, area, and development schedules.
Work closely with physical design teams to ensure RTL supports timing closure, power targets, and manufacturability on advanced process nodes.
Must-Have Skills
BS/MS in Electrical Engineering, Computer Engineering, or related field.
5+ years of hands‑on ASIC design experience with complex digital logic, particularly using SystemVerilog.
Demonstrated experience designing high performance compute and high-speed data transport logic.
Experience with fabric and high-speed IO integration (e.g., PCIe, HBM).
Proficiency with testbench creation, simulation environments, and synthesis flows.
Strong scripting abilities with Python, Perl, or TCL for design automation.
Self‑motivated with a track record of thriving in dynamic, start‑up environments.
Nice-to-Have Skills
Direct experience integrating open source IP for chiplet architectures.
Background in AI inference or building silicon solutions for AI/ML applications.
Experience developing automation around performance, power, and area trade‑offs.
Expertise in technical documentation, specification writing, and design reviews.
Familiarity with advanced process nodes and optimization for manufacturability.
Prior exposure to collaborative start‑up environments and multidisciplinary engineering teams.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Design
Industries Technology, Information and Media and Semiconductor Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
Referrals increase your chances of interviewing at Talently by 2x
#J-18808-Ljbffr