Senior High-Speed SerDes Architect | Multi-Lane IP

A leading tech company in San Francisco is seeking an experienced Analog/RF IC Designer to develop high-speed SerDes interfaces. This role involves defining and verifying cores that exceed 25Gb/s, and mentoring junior engineers. Candidates should have 7+ years in high-speed design and a Bachelor's degree in Electrical Engineering. Competitive compensation ranges from $194,000 to $270,000, along with stock options and generous benefits including 33 days of paid time off. #J-18808-Ljbffr