Inherent Technologies
FPGA Verification Engineer
Location: Santa Clara, CA (Onsite, 100% – Day 1 Mon-Fri)
Duration: 12+ months
Employment type: Full-time • Seniority level: Mid-Senior level
Responsibilities
Strong understanding of FPGA design principles and architectures.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem‑solving skills.
Strong communication and collaboration skills.
Qualifications
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Required Skills
8+ years of FPGA verification experience.
5+ years of UVM verification experience.
5+ years of System Verilog experience.
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Location: Santa Clara, CA (Onsite, 100% – Day 1 Mon-Fri)
Duration: 12+ months
Employment type: Full-time • Seniority level: Mid-Senior level
Responsibilities
Strong understanding of FPGA design principles and architectures.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem‑solving skills.
Strong communication and collaboration skills.
Qualifications
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Required Skills
8+ years of FPGA verification experience.
5+ years of UVM verification experience.
5+ years of System Verilog experience.
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