FPGA Verification Engineer

FPGA Verification Engineer – Mountain View, CA Must Have Skills – FPGA Verification Engineer

Skill 1 – 8 + Years of experience in FPGA

Skill 2 – 5 + Years of experience in UVM

Skill 3 – 5 + Years of experience in System Verilog

Onsite Requirement: Yes – 5 Days

Job Description

Strong understanding of FPGA design principles and architectures.

Proficiency in System Verilog and UVM verification methodology.

Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).

Knowledge of code coverage and functional coverage analysis.

Excellent debugging and problem-solving skills.

Strong communication and collaboration skills.

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.

Experience in FPGA verification. Experience with scripting languages (e.g., Python, Perl).

Familiarity with hardware description languages (e.g., VHDL, Verilog).

Seniority level

Mid-Senior level

Employment type

Contract

Job function

Quality Assurance

IT Services and IT Consulting

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