CyberCoders
Job Title
Sr. ASIC RTL Design Engineer
Job Location San Jose, CA or Irvine, CA
Compensation $150K - $250K base DOE plus equity
Requirements Logic Design, RTL, Processor Architecture, Memory, Cache Subsystems, NoC, Interconnects
Position Overview We are seeking a highly skilled Sr. ASIC RTL Design Engineer to join our innovative team. The ideal candidate will be responsible for designing and implementing complex ASIC designs, focusing on RTL development and ensuring high performance and efficiency in our next-generation products.
Key Responsibilities
Design and develop RTL for complex ASIC designs
Collaborate with cross-functional teams to define specifications and architecture
Perform logic design and data path design for various components
Optimize designs for performance, area, and power consumption
Conduct simulations and validations to ensure design functionality
Participate in design reviews and provide constructive feedback
Support the integration of memory and cache subsystems within the architecture
Work on interconnect architectures, including NOC solutions
Implement and verify floating-point arithmetic operations in design
Stay updated with industry trends and advancements in RISC-V architecture
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of experience in ASIC design and RTL development
Strong knowledge of logic design and RTL design methodologies
Experience with processor architecture and system design
Familiarity with memory and cache subsystems
Proficiency in interconnect design, including NOC
Hands-on experience with RISC-V architecture is a plus
Solid understanding of floating-point arithmetic and data path design is a plus
Benefits
Vacation/PTO
Equity
Medical
Vision
Life Insurance
401k
Additional Information Referrals increase your chances of interviewing at CyberCoders by 2x
#J-18808-Ljbffr
Job Location San Jose, CA or Irvine, CA
Compensation $150K - $250K base DOE plus equity
Requirements Logic Design, RTL, Processor Architecture, Memory, Cache Subsystems, NoC, Interconnects
Position Overview We are seeking a highly skilled Sr. ASIC RTL Design Engineer to join our innovative team. The ideal candidate will be responsible for designing and implementing complex ASIC designs, focusing on RTL development and ensuring high performance and efficiency in our next-generation products.
Key Responsibilities
Design and develop RTL for complex ASIC designs
Collaborate with cross-functional teams to define specifications and architecture
Perform logic design and data path design for various components
Optimize designs for performance, area, and power consumption
Conduct simulations and validations to ensure design functionality
Participate in design reviews and provide constructive feedback
Support the integration of memory and cache subsystems within the architecture
Work on interconnect architectures, including NOC solutions
Implement and verify floating-point arithmetic operations in design
Stay updated with industry trends and advancements in RISC-V architecture
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of experience in ASIC design and RTL development
Strong knowledge of logic design and RTL design methodologies
Experience with processor architecture and system design
Familiarity with memory and cache subsystems
Proficiency in interconnect design, including NOC
Hands-on experience with RISC-V architecture is a plus
Solid understanding of floating-point arithmetic and data path design is a plus
Benefits
Vacation/PTO
Equity
Medical
Vision
Life Insurance
401k
Additional Information Referrals increase your chances of interviewing at CyberCoders by 2x
#J-18808-Ljbffr