Senior FPGA Verification Engineer - SystemVerilog & UVM

A technology solutions company in California is seeking an experienced FPGA Verification Engineer. The ideal candidate will have a strong understanding of FPGA design, proficiency in System Verilog, and experience in verification methodologies such as UVM. Candidates should possess solid debugging skills and be familiar with various verification tools. A Bachelor's or Master's degree in Electrical Engineering or a related field is required, along with relevant experience in FPGA verification. #J-18808-Ljbffr