FPGA Verification Engineer — SystemVerilog/UVM Specialist

A leading IT services firm is seeking an experienced FPGA Verification Engineer to join their Mountain View team. The candidate should possess strong expertise in SystemVerilog and UVM, focusing on developing and executing verification strategies for complex FPGA designs. Responsibilities include verifying designs based on specifications, conducting functional coverage analysis, and collaborating with design engineers to resolve issues. A Bachelor's or Master's degree in Electrical or Computer Engineering is required, along with proven experience in FPGA verification and familiarity with verification tools. #J-18808-Ljbffr