Senior Verification Engineer - RTL & DRAM Memory Interfaces

A leading technology firm in Santa Clara is looking for a Logic Design Engineer to work on graphics memory controller development. The ideal candidate will have over five years of experience in digital design, proficiency in Verilog, and a background in high-speed memory interfaces. This role involves logic design and collaboration with verification engineers to enhance AMD's GPU and data center solutions. #J-18808-Ljbffr