Triple Crown
Senior Formal Verification Engineer
Triple Crown, Palo Alto, California, United States, 94306
Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place developers, architects, coders, and designers who engineer digital transformation and growth.
Job Type:
Contract
Duration:
3+ Months
Location:
Onsite in Palo Alto, CA or Austin, TX
Requirement:
6+ years of relevant experience
We are seeking a highly skilled
Formal Verification Engineer
to join our verification team and help drive high-quality sign-off for complex hardware designs. The ideal candidate has strong experience with formal verification tools (VC Formal or JasperGold), deep understanding of SystemVerilog Assertions (SVA), and the ability to define and execute verification strategies for robust verification closure.
Responsibilities
Define comprehensive formal verification plans, strategies, and methodologies to achieve high-quality verification sign-off.
Review and contribute to RTL design architecture and specifications to ensure formal verifiability.
Develop and prove SystemVerilog Assertions (SVA) to validate design intent and corner cases.
Use formal verification techniques—including model checking, logical equivalence checking, and theorem proving—to prove functional correctness of design features.
Collaborate with simulation teams to provide formal sign-off and ensure full verification closure for IP blocks and subsystems.
Build, enhance, and maintain regression environments, infrastructure, and tooling for formal verification workflows.
Analyze verification results, root‑cause failures, and provide actionable insights to design and architecture teams.
Support and improve integrated formal + simulation‑based verification methodologies across the organization.
Skills
SVA
RTL Design
Formal sign‑off
Verification Methodologies
Benefits
Health, Dental and Vision Insurance
401k
#J-18808-Ljbffr
Job Type:
Contract
Duration:
3+ Months
Location:
Onsite in Palo Alto, CA or Austin, TX
Requirement:
6+ years of relevant experience
We are seeking a highly skilled
Formal Verification Engineer
to join our verification team and help drive high-quality sign-off for complex hardware designs. The ideal candidate has strong experience with formal verification tools (VC Formal or JasperGold), deep understanding of SystemVerilog Assertions (SVA), and the ability to define and execute verification strategies for robust verification closure.
Responsibilities
Define comprehensive formal verification plans, strategies, and methodologies to achieve high-quality verification sign-off.
Review and contribute to RTL design architecture and specifications to ensure formal verifiability.
Develop and prove SystemVerilog Assertions (SVA) to validate design intent and corner cases.
Use formal verification techniques—including model checking, logical equivalence checking, and theorem proving—to prove functional correctness of design features.
Collaborate with simulation teams to provide formal sign-off and ensure full verification closure for IP blocks and subsystems.
Build, enhance, and maintain regression environments, infrastructure, and tooling for formal verification workflows.
Analyze verification results, root‑cause failures, and provide actionable insights to design and architecture teams.
Support and improve integrated formal + simulation‑based verification methodologies across the organization.
Skills
SVA
RTL Design
Formal sign‑off
Verification Methodologies
Benefits
Health, Dental and Vision Insurance
401k
#J-18808-Ljbffr