Senior Emulation Engineer for Networking ASICs

A leading technology company in San Jose is seeking a Verification Engineer with over 8 years of experience in pre-silicon verification of networking ASICs. The role involves developing comprehensive test plans and collaborating with cross-functional teams. Compensation ranges from $120,000 to $192,000 annually, alongside a comprehensive benefits package. Ideal candidates should have strong skills in C/C++, Verilog, and debugging, with experience in emulation platforms like Zebu or Palladium. #J-18808-Ljbffr