Lead Emulation Engineer, Networking ASICs

A leading technology company in San Jose is looking for a Pre-Silicon Verification Engineer to define and develop test plans for networking ASICs. The ideal candidate has over 8 years of experience, strong skills in Verilog/SystemVerilog, C/C++, Tcl, and Python, and a collaborative approach to problem-solving. This role offers a competitive salary with comprehensive benefits and opportunities for growth. #J-18808-Ljbffr