Broadcom
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DFT Engineer
role at
Broadcom
Job Description Broadcom’s CSG division is seeking a candidate for a DFT lead position. The successful candidate will be responsible for leading the most complex and cutting‑edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture to implementation, verification, timing closure, and ATE pattern bring‑up. You will also drive/push state of the art in the areas of testability, debug, and quality, in order to aggressively deliver low DPPM's while optimizing the cost for test.
Responsibilities
Drive the test quality of the products from Design to Production
Participate/contribute in silicon bring‑up, characterization, and silicon test
Define and implement various DFx features
Requirements
Knowledge of Testability techniques and features (SCAN, Built‑in‑Self‑Tests, Loop‑Backs, etc.) covering digital logic domain, embedded memories and PHY/IO’s
Scan flow development, ATPG pattern generation, verification and coverage analysis
Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification
Experience working with Cadence DFT tools (Modus and Genus)
Well‑versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
Strong knowledge of logic & circuit design fundamentals is needed
Working knowledge of TCL, Perl
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
Experience or working knowledge of SERDES, Analog/mixed‑signal DFT techniques (like IOBIST, loop‑backs, etc.) is a plus
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a must
Post‑silicon experience in Pattern conversion for Testers, Pattern Bring‑up & Debug, Silicon Characterization, etc. is a plus
Experience or familiarity in back‑end chip design, Timing, CDC flows is a plus
Strong pre/post‑silicon debugging, analytical and independent problem‑solving ability.
Must be a team player with good verbal and written communication skills.
Must be self‑driven engineer with good project management and organizational skills to deliver high‑quality output in a timely manner.
Experience: Bachelor's and 8+ years of related experience
Compensation and Benefits The annual base salary range for this position is $120,000 - $192,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Information Technology
Industries Semiconductor Manufacturing
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DFT Engineer
role at
Broadcom
Job Description Broadcom’s CSG division is seeking a candidate for a DFT lead position. The successful candidate will be responsible for leading the most complex and cutting‑edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture to implementation, verification, timing closure, and ATE pattern bring‑up. You will also drive/push state of the art in the areas of testability, debug, and quality, in order to aggressively deliver low DPPM's while optimizing the cost for test.
Responsibilities
Drive the test quality of the products from Design to Production
Participate/contribute in silicon bring‑up, characterization, and silicon test
Define and implement various DFx features
Requirements
Knowledge of Testability techniques and features (SCAN, Built‑in‑Self‑Tests, Loop‑Backs, etc.) covering digital logic domain, embedded memories and PHY/IO’s
Scan flow development, ATPG pattern generation, verification and coverage analysis
Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification
Experience working with Cadence DFT tools (Modus and Genus)
Well‑versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
Strong knowledge of logic & circuit design fundamentals is needed
Working knowledge of TCL, Perl
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
Experience or working knowledge of SERDES, Analog/mixed‑signal DFT techniques (like IOBIST, loop‑backs, etc.) is a plus
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a must
Post‑silicon experience in Pattern conversion for Testers, Pattern Bring‑up & Debug, Silicon Characterization, etc. is a plus
Experience or familiarity in back‑end chip design, Timing, CDC flows is a plus
Strong pre/post‑silicon debugging, analytical and independent problem‑solving ability.
Must be a team player with good verbal and written communication skills.
Must be self‑driven engineer with good project management and organizational skills to deliver high‑quality output in a timely manner.
Experience: Bachelor's and 8+ years of related experience
Compensation and Benefits The annual base salary range for this position is $120,000 - $192,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Information Technology
Industries Semiconductor Manufacturing
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