Broadcom
Join to apply for the
DFT Engineer
role at
Broadcom .
Overview Broadcom’s CSG division is seeking a candidate for a DFT lead position. The successful candidate will be responsible for leading the most complex and cutting‑edge network switching ASIC DFx (Design for Test/Debug & Manufacturability) from DFT architecture to implementation, verification, timing closure, and ATE pattern bring‑up. You will also drive state‑of‑the‑art testability, debug, and quality to aggressively deliver low DPPM’s while optimizing the cost for test.
Responsibilities
Drive the test quality of the products from Design to Production
Participate/contribute in silicon bring‑up, characterization, and silicon test
Define and implement various DFx features
Requirements
Knowledge of testability techniques and features (SCAN, Built‑in‑Self‑Tests, Loop‑Backs, etc.) covering digital logic domain, embedded memories and PHY/IO’s
Scan flow development, ATPG pattern generation, verification and coverage analysis
Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification
Experience working with Cadence DFT tools (Modus and Genus)
Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
Strong knowledge of logic & circuit design fundamentals is needed
Working knowledge of TCL, Perl
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
Experience or working knowledge of SERDES, analog/mixed‑signal DFT techniques (like IOBIST, loop‑backs, etc.) is a plus
Post‑silicon experience in pattern conversion for testers, pattern bring‑up & debug, silicon characterization, etc. is a plus
Experience or familiarity in back‑end chip design, timing, CDC flows is a plus
Strong pre/post silicon debugging, analytical and independent problem‑solving ability
Must be a team player with good verbal and written communication skills
Must be self‑driven with good project management and organizational skills to deliver high‑quality output in a timely manner
Bachelors degree and 8+ years of related experience
Compensation & Benefits The annual base salary range for this position is $120,000 – $192,000. This position is also eligible for a discretionary annual bonus, equity, and a comprehensive benefits package: medical, dental, vision, 401(k) with company match, ESPP, EAP, holidays, paid sick leave, vacation time, and compliance with all applicable Paid Family Leave laws.
#J-18808-Ljbffr
DFT Engineer
role at
Broadcom .
Overview Broadcom’s CSG division is seeking a candidate for a DFT lead position. The successful candidate will be responsible for leading the most complex and cutting‑edge network switching ASIC DFx (Design for Test/Debug & Manufacturability) from DFT architecture to implementation, verification, timing closure, and ATE pattern bring‑up. You will also drive state‑of‑the‑art testability, debug, and quality to aggressively deliver low DPPM’s while optimizing the cost for test.
Responsibilities
Drive the test quality of the products from Design to Production
Participate/contribute in silicon bring‑up, characterization, and silicon test
Define and implement various DFx features
Requirements
Knowledge of testability techniques and features (SCAN, Built‑in‑Self‑Tests, Loop‑Backs, etc.) covering digital logic domain, embedded memories and PHY/IO’s
Scan flow development, ATPG pattern generation, verification and coverage analysis
Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification
Experience working with Cadence DFT tools (Modus and Genus)
Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
Strong knowledge of logic & circuit design fundamentals is needed
Working knowledge of TCL, Perl
Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
Experience or working knowledge of SERDES, analog/mixed‑signal DFT techniques (like IOBIST, loop‑backs, etc.) is a plus
Post‑silicon experience in pattern conversion for testers, pattern bring‑up & debug, silicon characterization, etc. is a plus
Experience or familiarity in back‑end chip design, timing, CDC flows is a plus
Strong pre/post silicon debugging, analytical and independent problem‑solving ability
Must be a team player with good verbal and written communication skills
Must be self‑driven with good project management and organizational skills to deliver high‑quality output in a timely manner
Bachelors degree and 8+ years of related experience
Compensation & Benefits The annual base salary range for this position is $120,000 – $192,000. This position is also eligible for a discretionary annual bonus, equity, and a comprehensive benefits package: medical, dental, vision, 401(k) with company match, ESPP, EAP, holidays, paid sick leave, vacation time, and compliance with all applicable Paid Family Leave laws.
#J-18808-Ljbffr