Principal ASIC Verification Engineer, Cybersecurity Firewall

A cybersecurity company is seeking a Design Verification engineer to join their ASIC team in Santa Clara, California. The role requires strong expertise in SystemVerilog, UVM, and Python programming. The engineer will collaborate with various engineering teams to ensure the quality and reliability of innovative cybersecurity products. With a base salary expected between $235,000 - $260,000, this position offers an opportunity to work in a dynamic environment committed to preventing cyberattacks. #J-18808-Ljbffr