DFT Design Engineer: RTL & MBIST Expert for SoC

A leading technology company is seeking a DFT Design Engineer to develop and optimize logic design and provide DFT support. The successful candidate will have experience with DFT Array Test, including MBIST or Scan/ATPG. Qualifications include a Bachelor's degree in a relevant field and at least 4 years of relevant experience. This position offers competitive compensation and is based in Santa Clara, California, with an on-site work model. #J-18808-Ljbffr