Senior RTL Networking Architect: Packet Buffering & QoS

A Silicon Valley hardware startup is looking for an experienced RTL Packet Buffering engineer to design and implement cutting-edge Networking IC solutions. This role includes responsibilities such as designing high-speed networking chips with a focus on latency optimization and protocol support. The ideal candidate has 8-15 years of experience and works proficiently with SystemVerilog and Verilog, contributing to the evolution of AI networking infrastructure. Competitive salary offered in the range of $210,000 - $275,000 per year. #J-18808-Ljbffr