Senior RTL Networking ASIC Engineer — AI Infrastructure

A leading semiconductor company is seeking experienced RTL designers to contribute to innovative AI networking solutions. This role involves defining and implementing cutting-edge Networking ASICs, focusing on packet buffering and performance optimization. Candidates should have significant experience in ASIC methodologies and proficiency in SystemVerilog and Verilog. The ideal candidate will work with high-speed networking protocols and collaborate within a cross-functional team. Join us in transforming AI infrastructure and pushing technological boundaries. #J-18808-Ljbffr