Senior Staff DV Architect for CPU Cluster SoC

A leading technology company is seeking candidates for a role focused on building verification infrastructure for high-performance RISC-V CPU clusters. This position involves defining verification plans and driving coverage closure for complex SoCs. Ideal candidates will have substantial experience with SystemVerilog and UVM, along with a Bachelor's or Master's degree in Electrical Engineering. The compensation range is competitive, starting at $100k and may go up to $500k. #J-18808-Ljbffr