OSI Engineering, Inc.
Sr. Manager Validation Engineering
OSI Engineering, Inc., San Jose, California, United States, 95199
A leading chip and silicon IP provider is seeking an experienced Validation Manager to join its Memory Interface Chip business unit. In this role, you ll collaborate with some of the industry s top engineers and innovators to develop products that make data faster, more efficient, and more secure.
This is a hands-on technical management role and requires approximately 20 30% day-to-day technical work alongside leadership responsibilities.
Key Focus Areas & Technical Expertise
Bench validation and electrical characterization of high-performance memory buffer chips
DDR4/DDR5 memory characterization and validation
Strong Python coding skills must be capable of developing automation scripts and lab tools
Experience with SerDes or PCIe/PCIe PHY high-speed interfaces
Solid understanding of signal integrity, power integrity, and high-speed I/O characterization
Responsibilities
Lead and directly contribute to hands-on bench validation and electrical characterization activities (20 30% of time)
Manage and mentor a small team of 2 5 validation engineers, ensuring technical excellence and project alignment
Partner with Design, Architecture, Verification, and Operations teams to deliver top-quality buffer chip products
Develop and continuously refine validation methodologies, improving design coverage, efficiency, and time-to-market
Collaborate with internal and external partners for test equipment sourcing, PCB fabrication, and assembly
Develop automation frameworks and Python-based validation scripts for data collection and analysis
Define and execute test methodologies to validate silicon designs against specifications
Contribute to project planning, budgeting, and resource allocation
Qualifications
B.S. or M.S. in Electrical Engineering or related field
Proven experience with DDR4/DDR5 memory interfaces and processor/memory system architectures
Demonstrated proficiency in Python scripting for validation, automation, and data analysis
Background in SerDes or PCIe PHY characterization is highly desired
Strong understanding of electrical characterization, signal integrity, and power integrity
Experience managing small teams or leading technical projects as an individual contributor with leadership responsibilities
Experience with ATE or system-level testing is a plus
Excellent communication, organizational, and cross-functional collaboration skills
Location Atlanta, GA; San Jose, CA; United States
Duration Fulltime
Salary Range $170-$210K (DOE)
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This is a hands-on technical management role and requires approximately 20 30% day-to-day technical work alongside leadership responsibilities.
Key Focus Areas & Technical Expertise
Bench validation and electrical characterization of high-performance memory buffer chips
DDR4/DDR5 memory characterization and validation
Strong Python coding skills must be capable of developing automation scripts and lab tools
Experience with SerDes or PCIe/PCIe PHY high-speed interfaces
Solid understanding of signal integrity, power integrity, and high-speed I/O characterization
Responsibilities
Lead and directly contribute to hands-on bench validation and electrical characterization activities (20 30% of time)
Manage and mentor a small team of 2 5 validation engineers, ensuring technical excellence and project alignment
Partner with Design, Architecture, Verification, and Operations teams to deliver top-quality buffer chip products
Develop and continuously refine validation methodologies, improving design coverage, efficiency, and time-to-market
Collaborate with internal and external partners for test equipment sourcing, PCB fabrication, and assembly
Develop automation frameworks and Python-based validation scripts for data collection and analysis
Define and execute test methodologies to validate silicon designs against specifications
Contribute to project planning, budgeting, and resource allocation
Qualifications
B.S. or M.S. in Electrical Engineering or related field
Proven experience with DDR4/DDR5 memory interfaces and processor/memory system architectures
Demonstrated proficiency in Python scripting for validation, automation, and data analysis
Background in SerDes or PCIe PHY characterization is highly desired
Strong understanding of electrical characterization, signal integrity, and power integrity
Experience managing small teams or leading technical projects as an individual contributor with leadership responsibilities
Experience with ATE or system-level testing is a plus
Excellent communication, organizational, and cross-functional collaboration skills
Location Atlanta, GA; San Jose, CA; United States
Duration Fulltime
Salary Range $170-$210K (DOE)
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