Memory Interface Validation Lead (DDR4/5, SerDes)

A leading chip provider is seeking an experienced Validation Manager to join its Memory Interface Chip business unit in San Jose, CA. This hands-on role involves bench validation and electrical characterization of high-performance memory buffer chips. Candidates should possess strong Python skills and experience with DDR4/DDR5 memory interfaces. Responsibilities include managing a small team, enhancing validation methodologies, and collaborating with cross-functional teams. Competitive salary range of $170-$210K depending on experience is offered. #J-18808-Ljbffr