Cisco Systems, Inc.
Who we are
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non‑Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best‑of‑breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
Your Impact You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front‑end RTL teams, backend physical design teams to understand chip architecture and drive high‑quality DFT verification.
Key Essential Functions
Responsible for thorough test planning and development of test benches to verify comprehensive Design‑for‑Test (DFT) architecture that supports ATE screening, in‑system test, debug and diagnostics needs of the design.
Collaborate with the design/design‑verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re‑usable test and debug methodologies and standards.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Qualifications
Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
Prior experience in test planning based on complex design specification.
Prior experience in testbench development using System Verilog.
Debugging experience using DVE/Verdi.
Scripting skills: Tcl, Python/Perl.
Preferred Qualifications
UVM and advanced System Verilog knowledge.
Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.
Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
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Your Impact You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front‑end RTL teams, backend physical design teams to understand chip architecture and drive high‑quality DFT verification.
Key Essential Functions
Responsible for thorough test planning and development of test benches to verify comprehensive Design‑for‑Test (DFT) architecture that supports ATE screening, in‑system test, debug and diagnostics needs of the design.
Collaborate with the design/design‑verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re‑usable test and debug methodologies and standards.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Qualifications
Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
Prior experience in test planning based on complex design specification.
Prior experience in testbench development using System Verilog.
Debugging experience using DVE/Verdi.
Scripting skills: Tcl, Python/Perl.
Preferred Qualifications
UVM and advanced System Verilog knowledge.
Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.
Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
#J-18808-Ljbffr