Advanced Micro Devices, Inc.
Interconnect RTL Design Engineer
Advanced Micro Devices, Inc., Santa Clara, California, us, 95053
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
THE ROLE: As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation scalable coherent interconnect to provide connectivity between CPU, GPU and special purpose accelerators. Every product that AMD sells has its own custom‑designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer‑specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!
THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Early architectural/performance exploration through micro‑architectural definition and design
Optimize the design to meet power, performance, area and timing requirements
Write easily readable and synthesizable System Verilog RTL
Run unit level testing to deliver quality code to the Design Verification Team
Create assertions to improve coverage and cover points to analyze coverage of the design
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Create hardware emulation build to verify the IP functional performance
Create well written block level design documentation
Participate in post‑silicon functional and performance debug and tuning
Provide technical support to other teams such as verification and physical design teams
Mentor junior engineers
PREFERRED EXPERIENCE:
Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs
Strong understanding of digital electronics and high‑speed designs (>1GHz)
Strong understanding of multi‑processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches
Excellent knowledge of Verilog and System Verilog
Good debugging and analytical skills
Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
Working knowledge of C, C++ and a scripting language like Perl or Python
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Computer Engineering or Electrical Engineering
LOCATION:
Santa Clara, CA
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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Together, we advance your career.
THE ROLE: As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation scalable coherent interconnect to provide connectivity between CPU, GPU and special purpose accelerators. Every product that AMD sells has its own custom‑designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer‑specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team!
THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Early architectural/performance exploration through micro‑architectural definition and design
Optimize the design to meet power, performance, area and timing requirements
Write easily readable and synthesizable System Verilog RTL
Run unit level testing to deliver quality code to the Design Verification Team
Create assertions to improve coverage and cover points to analyze coverage of the design
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Create hardware emulation build to verify the IP functional performance
Create well written block level design documentation
Participate in post‑silicon functional and performance debug and tuning
Provide technical support to other teams such as verification and physical design teams
Mentor junior engineers
PREFERRED EXPERIENCE:
Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs
Strong understanding of digital electronics and high‑speed designs (>1GHz)
Strong understanding of multi‑processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches
Excellent knowledge of Verilog and System Verilog
Good debugging and analytical skills
Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
Working knowledge of C, C++ and a scripting language like Perl or Python
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Computer Engineering or Electrical Engineering
LOCATION:
Santa Clara, CA
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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