Senior TSV Packaging Design Engineer - FEA & Multiphysics

A leading semiconductor company located in Boise, Idaho, is seeking an experienced Design Engineer to join their TSV Packaging team. The successful candidate will innovate in packaging technologies for high-performance memory devices. Responsibilities include collaboration with global teams and development of semiconductor packages using advanced simulation tools. Ideal applicants will have over 8 years of experience in mechanical analysis, strong knowledge of related engineering tools, and excellent team collaboration skills. The company offers competitive benefits and a commitment to employee growth. #J-18808-Ljbffr