SiFive
About SiFive
As the pioneers who introduced RISC‑V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications in the world. SiFive’s unrivaled compute platforms enable leading technology companies to innovate, optimize and deliver advanced solutions across AI, machine learning, automotive, data center, mobile, and consumer markets. Our teams collaborate to create groundbreaking ideas and solutions that have a huge impact on people’s lives, making the world a better place, one processor at a time. SiFive has won the GSA’s prestigious Most Respected Private Company Award for the fourth time.
Job Description SiFive seeks a hardware design technical lead focused on debug, trace and profiling IP for SOC designs across a broad variety of vertical applications. The role designs industry‑leading debug, trace and profiling hardware, leveraging the Chisel hardware construction library in Scala to build highly configurable generators. Enhanced collaboration with customers, partners, tools vendors and the RISC‑V International Association will shape the future of debug strategy.
Challenges
Design the best debug, trace, and profiling hardware in the world based on open RISC‑V and TileLink architectures.
Master designing hardware as configurable generators in a domain‑specific software language for elaborating digital logic.
Work in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Job Responsibilities
Architect, design and implement debug, trace and profiling hardware.
Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
Implement RTL generators so elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
Ensure knowledge is shared via creation and maintenance of great documentation and by participating in a culture of collaborative design.
Position Requirements
Knowledgeable in debug, trace and profiling architecture and concepts.
Knowledgeable in debug interfaces, JTAG, cJTAG.
Knowledgeable in CPU architectures, power management and SoC design.
Experience in debugging tools and profiling methods.
Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
Attention to detail and a focus on high‑quality design.
Ability to work well with others and a belief that engineering is a team sport.
Knowledge of at least one object‑oriented and/or functional programming language.
Knowledge of one or more of: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
MS/PhD in EE, CE, CS or a related technical discipline.
Pay & Benefits Base Pay Range: $193,500.00 – $236,500.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The position also offers a comprehensive benefits package that may include health care, retirement plans, paid time off and more.
Additional Information This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment is contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or that the necessary export licenses or approvals have been obtained.
SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm employment eligibility of all new hires in accordance with federal law. All applicants will complete a Form I‑9 upon hire.
California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights:
Privacy Policy Document .
#J-18808-Ljbffr
Job Description SiFive seeks a hardware design technical lead focused on debug, trace and profiling IP for SOC designs across a broad variety of vertical applications. The role designs industry‑leading debug, trace and profiling hardware, leveraging the Chisel hardware construction library in Scala to build highly configurable generators. Enhanced collaboration with customers, partners, tools vendors and the RISC‑V International Association will shape the future of debug strategy.
Challenges
Design the best debug, trace, and profiling hardware in the world based on open RISC‑V and TileLink architectures.
Master designing hardware as configurable generators in a domain‑specific software language for elaborating digital logic.
Work in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Job Responsibilities
Architect, design and implement debug, trace and profiling hardware.
Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
Implement RTL generators so elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
Ensure knowledge is shared via creation and maintenance of great documentation and by participating in a culture of collaborative design.
Position Requirements
Knowledgeable in debug, trace and profiling architecture and concepts.
Knowledgeable in debug interfaces, JTAG, cJTAG.
Knowledgeable in CPU architectures, power management and SoC design.
Experience in debugging tools and profiling methods.
Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
Attention to detail and a focus on high‑quality design.
Ability to work well with others and a belief that engineering is a team sport.
Knowledge of at least one object‑oriented and/or functional programming language.
Knowledge of one or more of: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
MS/PhD in EE, CE, CS or a related technical discipline.
Pay & Benefits Base Pay Range: $193,500.00 – $236,500.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The position also offers a comprehensive benefits package that may include health care, retirement plans, paid time off and more.
Additional Information This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment is contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or that the necessary export licenses or approvals have been obtained.
SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm employment eligibility of all new hires in accordance with federal law. All applicants will complete a Form I‑9 upon hire.
California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights:
Privacy Policy Document .
#J-18808-Ljbffr