Senior SoC/ASIC PD Engineer – Lead Tapeout & Signoff

A leading semiconductor company is searching for a Senior SoC/ASIC Physical Design Engineer in San Jose or Irvine, CA. This full-time role requires over 10 years of experience in ASIC design, strong RTL-to-GDSII skills, and expertise in leading implementations through closure. Candidates should have proficiency in Synopsys tools and scripting. The position offers competitive benefits, including equity, medical insurance, and relocation assistance with H1B visa sponsorship. Ideal for proactive collaborators with a data-driven mindset. #J-18808-Ljbffr