Tesla
ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware
Tesla, Palo Alto, California, United States, 94306
ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware
What To Expect
Tesla is accelerating the world's transition to sustainable energy with electric cars, solar and integrated renewable energy solutions for homes and businesses. As part of our AI Hardware team, you will contribute to the development of custom ASICs that power our groundbreaking AI systems, including those for autonomous driving and machine learning training. In this specialized role, you will focus on Ethernet IP integration, SoC clocking and reset architectures, and high-performance data paths within our custom ASICs. This role is located in Palo Alto, CA or Austin, TX. You will work closely with cross‑functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in AI applications.
Candidate is expected to implement and document microarchitecture specifications tailored to networking and SoC integration, define system‑level functional requirements for high‑speed data handling, and deliver high‑quality RTL designs optimized for AI workloads.
What You'll Do
Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high‑throughput data transfer in AI hardware systems
Develop and optimize SoC clocking architectures, including multi‑domain clock distribution, synchronization, and power‑efficient clock gating techniques
Architect and implement SoC reset mechanisms, including synchronous/asynchronous resets, reset domain crossing, and fault‑tolerant recovery strategies
Optimize high‑performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines
Integrate third‑party IPs, such as Ethernet controllers and high‑speed serdes, while managing interface protocols like AXI for efficient data movement
Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking‑focused subsystems
Perform synthesis, timing analysis, and power optimization to meet aggressive performance targets in high‑speed protocols
Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations
Document designs, specifications, and integration guidelines to support team collaboration and future iterations
Participate in design reviews, code reviews, and contribute to overall ASIC development flows for AI hardware
What You'll Bring
Degree in Electrical Engineering, Computer Engineering, or a related technical field (or equivalent experience)
3+ years of experience in ASIC RTL design using Verilog or SystemVerilog
Strong knowledge of Ethernet protocols (e.g., 10G/25G/100G Ethernet, MAC/PHY layers, and IEEE standards)
Expertise in high‑speed protocols, including PCIe, SerDes, or similar interfaces for data‑intensive applications
Solid understanding of networking concepts, such as switching, routing, QoS, and packet buffering
Hands‑on experience with DMA controllers and high‑performance memory access in SoC environments
Proven track record in designing high‑performance RTL for compute‑intensive or data‑heavy systems, with emphasis on pipelining and parallelism
Proficiency with AXI/AMBA bus protocols for on‑chip interconnects and IP integration
In‑depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi‑clock domain handling
Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains
Benefits
Aetna PPO and HSA plans – 2 medical plan options with $0 payroll deduction
Family‑building, fertility, adoption and surrogacy benefits
Dental (including orthodontic coverage) and vision plans, both with options with a $0 paycheck contribution
Company Paid HSA Contribution when enrolled in the High Deductible Aetna medical plan
Healthcare and Dependent Care Flexible Spending Accounts (FSA)
401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
Company paid Basic Life, AD&D, short‑term and long‑term disability insurance
Employee Assistance Program
Sick and Vacation time (Flex time for salary positions), and Paid Holidays
Back‑up childcare and parenting support resources
Voluntary benefits – critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
Weight Loss and Tobacco Cessation Programs
Tesla Babies program
Commuter benefits
Employee discounts and perks program
Expected Compensation $104,000 – $264,000/annual salary + cash and stock awards + benefits
Seniority Level
– Mid‑Senior level
Employment type
– Full‑time
Job Function
– Engineering and Information Technology
Referrals increase your chances of interviewing at Tesla by 2x
#J-18808-Ljbffr
What You'll Do
Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high‑throughput data transfer in AI hardware systems
Develop and optimize SoC clocking architectures, including multi‑domain clock distribution, synchronization, and power‑efficient clock gating techniques
Architect and implement SoC reset mechanisms, including synchronous/asynchronous resets, reset domain crossing, and fault‑tolerant recovery strategies
Optimize high‑performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines
Integrate third‑party IPs, such as Ethernet controllers and high‑speed serdes, while managing interface protocols like AXI for efficient data movement
Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking‑focused subsystems
Perform synthesis, timing analysis, and power optimization to meet aggressive performance targets in high‑speed protocols
Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations
Document designs, specifications, and integration guidelines to support team collaboration and future iterations
Participate in design reviews, code reviews, and contribute to overall ASIC development flows for AI hardware
What You'll Bring
Degree in Electrical Engineering, Computer Engineering, or a related technical field (or equivalent experience)
3+ years of experience in ASIC RTL design using Verilog or SystemVerilog
Strong knowledge of Ethernet protocols (e.g., 10G/25G/100G Ethernet, MAC/PHY layers, and IEEE standards)
Expertise in high‑speed protocols, including PCIe, SerDes, or similar interfaces for data‑intensive applications
Solid understanding of networking concepts, such as switching, routing, QoS, and packet buffering
Hands‑on experience with DMA controllers and high‑performance memory access in SoC environments
Proven track record in designing high‑performance RTL for compute‑intensive or data‑heavy systems, with emphasis on pipelining and parallelism
Proficiency with AXI/AMBA bus protocols for on‑chip interconnects and IP integration
In‑depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi‑clock domain handling
Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains
Benefits
Aetna PPO and HSA plans – 2 medical plan options with $0 payroll deduction
Family‑building, fertility, adoption and surrogacy benefits
Dental (including orthodontic coverage) and vision plans, both with options with a $0 paycheck contribution
Company Paid HSA Contribution when enrolled in the High Deductible Aetna medical plan
Healthcare and Dependent Care Flexible Spending Accounts (FSA)
401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
Company paid Basic Life, AD&D, short‑term and long‑term disability insurance
Employee Assistance Program
Sick and Vacation time (Flex time for salary positions), and Paid Holidays
Back‑up childcare and parenting support resources
Voluntary benefits – critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
Weight Loss and Tobacco Cessation Programs
Tesla Babies program
Commuter benefits
Employee discounts and perks program
Expected Compensation $104,000 – $264,000/annual salary + cash and stock awards + benefits
Seniority Level
– Mid‑Senior level
Employment type
– Full‑time
Job Function
– Engineering and Information Technology
Referrals increase your chances of interviewing at Tesla by 2x
#J-18808-Ljbffr