7Rays Semiconductors
Senior Validation Engineer
San Jose, CA $80,000.00-$110,000.00
Job Responsibilities
Architect and develop verification environment, testbench components, and reference models for designs at block and system level.
Develop a comprehensive test plan and implement test cases.
Verify design in block and chip-level environments using directed and constrained random testing, assertion-based verification, formal analysis, functional verification.
Perform RTL code coverage, assertion coverage, and gate-level simulations.
Job Requirements
BS in Electrical Engineering, Computer Science, or related field with 12+ years of Industry experience or MS in Electrical Engineering, Computer Science, or related field preferred with 10+ years industry experience.
Experience in verifying designs at block and system level.
Experience using System Verilog and UVM.
Strong experience in ASIC design verification flows and DV methodologies.
Experience working with cross-functional teams to deliver ASICs from architecture to FCS.
Strong programming and scripting language (C/C++/Python etc.) capability.
Strong and independent design debugging capability.
Domain knowledge of Ethernet, PCIe, and Switch Fabric is desirable.
Good problem-solving skills and the passion to take on challenges.
Highly motivated and able to work independently and as a team member.
Seniority level
Mid-Senior level
Employment type
Contract
Job function
Quality Assurance
Industries
Semiconductor Manufacturing
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Job Responsibilities
Architect and develop verification environment, testbench components, and reference models for designs at block and system level.
Develop a comprehensive test plan and implement test cases.
Verify design in block and chip-level environments using directed and constrained random testing, assertion-based verification, formal analysis, functional verification.
Perform RTL code coverage, assertion coverage, and gate-level simulations.
Job Requirements
BS in Electrical Engineering, Computer Science, or related field with 12+ years of Industry experience or MS in Electrical Engineering, Computer Science, or related field preferred with 10+ years industry experience.
Experience in verifying designs at block and system level.
Experience using System Verilog and UVM.
Strong experience in ASIC design verification flows and DV methodologies.
Experience working with cross-functional teams to deliver ASICs from architecture to FCS.
Strong programming and scripting language (C/C++/Python etc.) capability.
Strong and independent design debugging capability.
Domain knowledge of Ethernet, PCIe, and Switch Fabric is desirable.
Good problem-solving skills and the passion to take on challenges.
Highly motivated and able to work independently and as a team member.
Seniority level
Mid-Senior level
Employment type
Contract
Job function
Quality Assurance
Industries
Semiconductor Manufacturing
Sign in to set job alerts for “Senior Validation Engineer” roles. #J-18808-Ljbffr