Senior ASIC Design Implementation Engineer

A leading semiconductor company in San Jose seeks a Mid-Senior Level Engineer for design implementation related to place and route. Candidates should have 12+ years of experience in electrical or computer engineering with expertise in timing analysis. Responsibilities include implementing methodologies to achieve desired metrics and leading design processes. Competitive salary range from $141,300 to $226,000, along with comprehensive benefits including medical plans and a 401(K) match. #J-18808-Ljbffr