Memory Interconnect Architect — FPGA Systems Lead

A leading technology corporation in California seeks a highly skilled Senior Technical Staff Engineer - Architect (Memory Interconnect) to lead cross-functional teams in delivering high-performance integrations for FPGA products. The ideal candidate will have a Master's degree and over 12 years of experience in ASIC and FPGA development. Responsibilities include architecting solutions and working closely with various engineering disciplines to ensure product excellence. This role offers a competitive salary range of $88,000 to $232,000 based on experience. #J-18808-Ljbffr