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Quest Global

Senior Design Verification Engineer

Quest Global, Santa Clara, California, us, 95053

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This range is provided by Quest Global. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range $150,000.00/yr - $180,000.00/yr

Lead Technical Recruiter @ Quest Global | Talent Sourcing Who We Are:

Quest Global delivers world‑class end‑to‑end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi‑dimensional approach enables us to solve the most critical and large‑scale challenges across the aerospace & defense, automotive, energy, hi‑tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. The achievers and courageous challenge‑crushers we seek, have the following characteristics and skills.

We are seeking an experienced Design Verification Engineer who has at least 8 years of professional work experience with the following skill set:

Work Experience

Project experience with ARM‑based ecosystem components

M7, Coresight, NIC, and other AMBA bus interconnects

Familiarity with AMBA bus protocols and SoC system debug infrastructure

Understanding of SoC interfaces like QSPI, UART, GPIOs

Capable of working with multiple IP vendors and other IP teams

Strong experience with UVM based verification, setting up co‑simulation environments with ARM CPU models

Plus points: experience with DRAM memory controllers and its interfaces

Plus points: experience with UCIe

What will you do:

Work on HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows.

Perform constraint random verification, assertion writing, coverage analysis, debugging.

Work with ARM cores.

What You Will Bring:

Experience with verification tools such as UVM, System Verilog, and Verilog.

Strong understanding of semiconductor design and verification methodologies.

Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.

Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.

Seniority level Mid‑Senior level

Employment type Full‑time

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