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ASIC Design Engineer
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Jobs via Dice
Leading semiconductor manufacturer with competitive compensation, generous bonus, and stock options! Also offering relocation bonus and/or be willing to relocate to Atlanta, GA.
Salary: $125,000 - $200,000 per year.
About Us Leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets.
Benefits
Salary: $125,000 to $200,000
Annual performance-based bonus (10% to 15%)
Stock options
Hybrid work opportunity
Visa sponsorship and/or relocation bonus as needed
Job Details We are seeking a dynamic and motivated ASIC Design Engineer to join our team. This is a permanent position that offers the opportunity to work on innovative design projects, with a focus on ASIC development. The successful candidate will be part of a team responsible for all aspects of ASIC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Responsibilities
Define and develop ASICs using advanced hardware description languages.
Conduct RTL design and synthesis, timing analysis, and full chip integration.
Participate in the development of architecture and microarchitecture specifications.
Utilize your understanding of ASIC design flow to drive physical design and timing closure.
Conduct feasibility studies and propose design solutions for new features and capabilities.
Work closely with verification engineers to ensure first-pass silicon success.
Collaborate with other team members to resolve design and flow issues related to physical design, identify and help implement potential solutions.
Drive the development and execution of design and verification methodologies.
Contribute to the continuous improvement of ASIC design processes and methodologies.
Provide technical expertise and support to internal and external customers.
Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. A Master's degree is preferred.
Minimum of 5 years of experience in ASIC design and verification.
Proficiency in Verilog, SystemVerilog, TCL, Python, and Linux.
Experience with PMIC, Virtuoso, Innovis, SimVision, and Synopsys.
Strong understanding of ASIC design flow including RTL design, synthesis, place and route, and timing closure.
Familiarity with high-speed and low-power design techniques.
Excellent problem-solving skills and the ability to work in a team environment.
Strong communication skills, both written and verbal.
Ability to handle multiple tasks simultaneously and meet deadlines.
Self-motivated, with a strong desire to learn and stay updated with the latest in engineering technologies.
Equal Opportunity Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot's policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Required Information Privacy Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Jobot, and/or its agents and contracted partners.
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Engineering and Information Technology
Industries
Software Development
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ASIC Design Engineer
role at
Jobs via Dice
Leading semiconductor manufacturer with competitive compensation, generous bonus, and stock options! Also offering relocation bonus and/or be willing to relocate to Atlanta, GA.
Salary: $125,000 - $200,000 per year.
About Us Leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets.
Benefits
Salary: $125,000 to $200,000
Annual performance-based bonus (10% to 15%)
Stock options
Hybrid work opportunity
Visa sponsorship and/or relocation bonus as needed
Job Details We are seeking a dynamic and motivated ASIC Design Engineer to join our team. This is a permanent position that offers the opportunity to work on innovative design projects, with a focus on ASIC development. The successful candidate will be part of a team responsible for all aspects of ASIC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Responsibilities
Define and develop ASICs using advanced hardware description languages.
Conduct RTL design and synthesis, timing analysis, and full chip integration.
Participate in the development of architecture and microarchitecture specifications.
Utilize your understanding of ASIC design flow to drive physical design and timing closure.
Conduct feasibility studies and propose design solutions for new features and capabilities.
Work closely with verification engineers to ensure first-pass silicon success.
Collaborate with other team members to resolve design and flow issues related to physical design, identify and help implement potential solutions.
Drive the development and execution of design and verification methodologies.
Contribute to the continuous improvement of ASIC design processes and methodologies.
Provide technical expertise and support to internal and external customers.
Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. A Master's degree is preferred.
Minimum of 5 years of experience in ASIC design and verification.
Proficiency in Verilog, SystemVerilog, TCL, Python, and Linux.
Experience with PMIC, Virtuoso, Innovis, SimVision, and Synopsys.
Strong understanding of ASIC design flow including RTL design, synthesis, place and route, and timing closure.
Familiarity with high-speed and low-power design techniques.
Excellent problem-solving skills and the ability to work in a team environment.
Strong communication skills, both written and verbal.
Ability to handle multiple tasks simultaneously and meet deadlines.
Self-motivated, with a strong desire to learn and stay updated with the latest in engineering technologies.
Equal Opportunity Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot's policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Required Information Privacy Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Jobot, and/or its agents and contracted partners.
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Engineering and Information Technology
Industries
Software Development
#J-18808-Ljbffr