Apolis
This range is provided by Apolis. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $678.08/daily - $847.69/daily
Senior ASIC Engineer Santa Clara , CA 100% onsite work 12 months
Job Description Top 5 Required Skills Expert experience in C++ Programming Language Hands on experience with System Verilog Knowledge in AI ML (Artificial Intelligence Machine Learning) Experience with software productization Documentation, Debugging and Developer experience
Technologies C++ Programming Language System Verilog ASIC
Required Education Bachelors Degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration or related work experience Master’s Degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration or related work experience PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration or related work experience.
Responsibilities Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of highly complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for junior engineers.
Level of Responsibility Provides supervision/guidance to other team members. Decision‑making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively.
Seniority level Mid‑Senior level
Employment type Full‑time
Job Function Other and Manufacturing
Industries Semiconductor Manufacturing, Design Services, and Engineering Services
Referrals increase your chances of interviewing at Apolis by 2x
#J-18808-Ljbffr
Base pay range $678.08/daily - $847.69/daily
Senior ASIC Engineer Santa Clara , CA 100% onsite work 12 months
Job Description Top 5 Required Skills Expert experience in C++ Programming Language Hands on experience with System Verilog Knowledge in AI ML (Artificial Intelligence Machine Learning) Experience with software productization Documentation, Debugging and Developer experience
Technologies C++ Programming Language System Verilog ASIC
Required Education Bachelors Degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration or related work experience Master’s Degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration or related work experience PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration or related work experience.
Responsibilities Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of highly complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for junior engineers.
Level of Responsibility Provides supervision/guidance to other team members. Decision‑making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively.
Seniority level Mid‑Senior level
Employment type Full‑time
Job Function Other and Manufacturing
Industries Semiconductor Manufacturing, Design Services, and Engineering Services
Referrals increase your chances of interviewing at Apolis by 2x
#J-18808-Ljbffr