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Advanced Micro Devices

IP Design Verification Engineer

Advanced Micro Devices, Santa Clara, California, us, 95053

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WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career. THE ROLE We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug‑free designs.

THE PERSON You have a passion for digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

Collaborate with architects, hardware and firmware engineers to understand the features to be verified

Take ownership of different verification tasks

Define test plans, test benches, and tests using System Verilog and UVM

Debug RTL simulations and work with HW and FW development teams to verify fixes

Review functional and code coverage metrics to meet the coverage requirements

Develop and improve existing verification flows and environments

Provide technical support to other teams

PREFERRED EXPERIENCE

Proficient in IP level ASIC verification

Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE)

Working knowledge of Formal Verification methods and apps (FPV, CC, Sequence equivalence, etc.)

Proficient in debugging firmware and RTL code using simulation tools

Proficient in using UVM testbenches and working in Linux and Windows environment

Experienced with Verilog, System Verilog, C, and C++

Developing UVM based verification frameworks and testbenches, processes and flows

Automating workflows in a distributed compute environment

Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language

Good to have: prior experience with USB/PCIE/UFS Controllers.

ACADEMIC CREDENTIALS

Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION Santa Clara, Folsom, CA

BENEFITS Benefits offered are described: AMD benefits at a glance.

EQUAL OPPORTUNITY STATEMENT AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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