OSI Engineering
Semiconductor Test Development Engineer
OSI Engineering, San Jose, California, United States, 95199
A premier chip and silicon IP provider is seeking an exceptional Staff Test Engineer to join our Operations team in San Jose, CA.
This position offers a hybrid work model, with three days onsite each week and two days remote.
Responsibilities
Define the test plan and work with design to ensure good test coverage.
Communicate effectively with internal cross‑functional teams, customers, and suppliers.
Design ATE hardware for NPI support, including load board, probe card, and interface.
Manage the product life cycle from design and prototypes, through high‑volume manufacturing bring‑up, to RMA/sustaining support.
Optimize yield, test time, and multi‑site count.
Qualifications
B.S./M.S. in Electrical Engineering or equivalent experience.
Experience with test coverage and DFT (Scan/ATPG/JTAG/BIST).
Experience working with local and offshore OSATs.
In‑depth knowledge of Advantest V93k.
Experience with Smartest, Redhat, and GIT/SVN.
Ability to independently learn and problem‑solve.
Comfort with collaboration, open communication and reaching across functional borders.
Preferred Qualifications
Experience in DDR and high‑speed digital products.
Location San Jose, CA
Relocation Assistance Relocation assistance will be provided and will be based on your current location.
Schedule 3 days onsite, 2 days remote.
Salary Up to ~$177K (dependent on experience).
Seniority Level Mid‑Senior level
Employment Type Full‑time
Industry Semiconductor Manufacturing
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This position offers a hybrid work model, with three days onsite each week and two days remote.
Responsibilities
Define the test plan and work with design to ensure good test coverage.
Communicate effectively with internal cross‑functional teams, customers, and suppliers.
Design ATE hardware for NPI support, including load board, probe card, and interface.
Manage the product life cycle from design and prototypes, through high‑volume manufacturing bring‑up, to RMA/sustaining support.
Optimize yield, test time, and multi‑site count.
Qualifications
B.S./M.S. in Electrical Engineering or equivalent experience.
Experience with test coverage and DFT (Scan/ATPG/JTAG/BIST).
Experience working with local and offshore OSATs.
In‑depth knowledge of Advantest V93k.
Experience with Smartest, Redhat, and GIT/SVN.
Ability to independently learn and problem‑solve.
Comfort with collaboration, open communication and reaching across functional borders.
Preferred Qualifications
Experience in DDR and high‑speed digital products.
Location San Jose, CA
Relocation Assistance Relocation assistance will be provided and will be based on your current location.
Schedule 3 days onsite, 2 days remote.
Salary Up to ~$177K (dependent on experience).
Seniority Level Mid‑Senior level
Employment Type Full‑time
Industry Semiconductor Manufacturing
#J-18808-Ljbffr