Jobs via Dice
Principal Analog IC Design Engineers
Jobs via Dice, Camarillo, California, United States, 93012
Kforce's client, a rapidly growing and well-established semiconductor company, is seeking several Principal Analog IC Design Engineers to join their team. The position is 100% onsite.
Responsibilities
Drive active circuit design and provide technical leadership across projects
Design advanced TIAs using SiGe BiCMOS and FinFET CMOS technologies, achieving performance beyond industry benchmarks
Develop millimeter-wave transmission line structures for superior signal integrity
Create high-performance broadband analog circuits for optical front-end receivers
Design supporting analog blocks such as linear regulators, Aloops, sensors, and bandgap references
Define microarchitecture for major circuit blocks and guide implementation by the design team
Collaborate cross-functionally on post-silicon validation, qualification, mass production, and customer engagement
Requirements
Bachelor's degree in Electrical Engineering with 8-12+ years of relevant experience, or a Master's or PhD with 5-8+ years of experience in high-performance RF/Analog Receiver, TIA, Driver, or RFIC design
Proven track record in chip tape-out and lab evaluation of high-performance receivers
Proficiency with EDA CAD tools and hands‑on IC performance measurement/debugging
Strong foundation in transistor-level design, device physics, and control/feedback loop stability analysis
Preferred Skills
Expertise in multiple technologies, especially SiGe BiCMOS and FinFET CMOS
Experience designing physical layer ICs for high-speed optical fiber data communication
Leadership experience mentoring junior designers and serving as chip lead
Successful history of taking chips to mass production
Ability to translate chip-level specifications into architectural designs
Analog custom layout experience
Bonus Expertise
Aloop design
High‑precision analog circuits (linear regulators, current sensors, bandgaps, drivers, DAC/ADC)
Continuous‑time linear equalizers
Pay Range and Compensation The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors such as relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.
Benefits We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.
Equal Opportunity Statement Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
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Responsibilities
Drive active circuit design and provide technical leadership across projects
Design advanced TIAs using SiGe BiCMOS and FinFET CMOS technologies, achieving performance beyond industry benchmarks
Develop millimeter-wave transmission line structures for superior signal integrity
Create high-performance broadband analog circuits for optical front-end receivers
Design supporting analog blocks such as linear regulators, Aloops, sensors, and bandgap references
Define microarchitecture for major circuit blocks and guide implementation by the design team
Collaborate cross-functionally on post-silicon validation, qualification, mass production, and customer engagement
Requirements
Bachelor's degree in Electrical Engineering with 8-12+ years of relevant experience, or a Master's or PhD with 5-8+ years of experience in high-performance RF/Analog Receiver, TIA, Driver, or RFIC design
Proven track record in chip tape-out and lab evaluation of high-performance receivers
Proficiency with EDA CAD tools and hands‑on IC performance measurement/debugging
Strong foundation in transistor-level design, device physics, and control/feedback loop stability analysis
Preferred Skills
Expertise in multiple technologies, especially SiGe BiCMOS and FinFET CMOS
Experience designing physical layer ICs for high-speed optical fiber data communication
Leadership experience mentoring junior designers and serving as chip lead
Successful history of taking chips to mass production
Ability to translate chip-level specifications into architectural designs
Analog custom layout experience
Bonus Expertise
Aloop design
High‑precision analog circuits (linear regulators, current sensors, bandgaps, drivers, DAC/ADC)
Continuous‑time linear equalizers
Pay Range and Compensation The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors such as relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.
Benefits We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.
Equal Opportunity Statement Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
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