Sigmaways Inc
Great Opportunity to work on cutting edge RISC-V and FPGA based compute platforms!
We are seeking an experienced
FPGA Engineer
with deep expertise in
Xilinx FPGAs
and hands on experience integrating and mapping
SiFive RISC-V cores
onto FPGA platforms. The ideal candidate will play a key role in prototyping, validating and optimizing SoC architectures for high performance and energy efficient computing platforms.
Responsibilities
Design, implement, and debug FPGA based systems using Xilinx FPGA platforms (UltraScale / UltraScale+ / Versal is preferred.
Map, integrate and validate SiFive RISC-V cores into FPGA designs.
Customize and configure RISC-V cores, interconnects, memory subsystems, and peripherals.
Develop and optimize FPGA designs using
Vivado ,
Vitis , and related Xilinx toolchains.
Implement AXI-based interconnects and manage clocking, resets, and timing closure.
Perform functional verification, synthesis, place & route, and timing analysis.
Debug hardware and software interaction using simulation tools, logic analyzers, and on-chip debug features.
Collaborate with architecture, software and ASIC teams to transition FPGA prototypes to silicon.
Optimize designs for performance, power, and area (PPA).
Document architecture, design decisions, and validation results.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
At least 5 years of experience in FPGA design and development.
Strong hands on experience with Xilinx FPGAs and toolchains using Vivado, Vitis, SDK.
Proven experience mapping or integrating SiFive RISC-V cores into FPGA designs.
Strong proficiency in Verilog/System Verilog and/or VHDL.
Experience with AXI, AHB, and other standard SoC bus protocols.
Solid understanding of SoC architecture, memory controllers and peripherals.
Experience with FPGA based system bring up and debugging.
Familiarity with Linux or RTOS bring-up on RISC-V platforms.
Experience with RISC-V customization and extensions is a plus.
Knowledge of FPGA prototyping for ASIC development.
Experience with PCIe, Ethernet, DDR, HBM or high-speed interfaces is a plus.
Familiarity with UVM, simulation and formal verification.
Scripting experience with Python, Tcl, Bash for build and automation flows is a plus.
Exposure to power optimization and performance tuning on FPGA platforms.
Seniority Level Mid-Senior level
Employment Type Full-time
Job Function Design
Industries Semiconductor Manufacturing
#J-18808-Ljbffr
We are seeking an experienced
FPGA Engineer
with deep expertise in
Xilinx FPGAs
and hands on experience integrating and mapping
SiFive RISC-V cores
onto FPGA platforms. The ideal candidate will play a key role in prototyping, validating and optimizing SoC architectures for high performance and energy efficient computing platforms.
Responsibilities
Design, implement, and debug FPGA based systems using Xilinx FPGA platforms (UltraScale / UltraScale+ / Versal is preferred.
Map, integrate and validate SiFive RISC-V cores into FPGA designs.
Customize and configure RISC-V cores, interconnects, memory subsystems, and peripherals.
Develop and optimize FPGA designs using
Vivado ,
Vitis , and related Xilinx toolchains.
Implement AXI-based interconnects and manage clocking, resets, and timing closure.
Perform functional verification, synthesis, place & route, and timing analysis.
Debug hardware and software interaction using simulation tools, logic analyzers, and on-chip debug features.
Collaborate with architecture, software and ASIC teams to transition FPGA prototypes to silicon.
Optimize designs for performance, power, and area (PPA).
Document architecture, design decisions, and validation results.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
At least 5 years of experience in FPGA design and development.
Strong hands on experience with Xilinx FPGAs and toolchains using Vivado, Vitis, SDK.
Proven experience mapping or integrating SiFive RISC-V cores into FPGA designs.
Strong proficiency in Verilog/System Verilog and/or VHDL.
Experience with AXI, AHB, and other standard SoC bus protocols.
Solid understanding of SoC architecture, memory controllers and peripherals.
Experience with FPGA based system bring up and debugging.
Familiarity with Linux or RTOS bring-up on RISC-V platforms.
Experience with RISC-V customization and extensions is a plus.
Knowledge of FPGA prototyping for ASIC development.
Experience with PCIe, Ethernet, DDR, HBM or high-speed interfaces is a plus.
Familiarity with UVM, simulation and formal verification.
Scripting experience with Python, Tcl, Bash for build and automation flows is a plus.
Exposure to power optimization and performance tuning on FPGA platforms.
Seniority Level Mid-Senior level
Employment Type Full-time
Job Function Design
Industries Semiconductor Manufacturing
#J-18808-Ljbffr