Design Engineer: IC Layout, DRC/LVS & Timing ECOs

A leading semiconductor foundry is seeking a Design Engineer in San Jose, CA. Responsibilities include design rule checks and error fixes in advanced chip implementation. The ideal candidate holds a Master’s in Electrical Engineering and has experience with EDA tools like Innovus and Virtuoso, along with proficiency in Perl/TCL programming. This role offers a competitive salary range of $156k to $157k, with work performed in and around Santa Clara County. #J-18808-Ljbffr