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SoC Design Engineer
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OMNIVISION . Get AI-powered advice on this job and more exclusive features. Responsibilities
Be responsible for digital design of image sensor, SoC integration, and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure, and DFT. Conduct image sensor array/analog related timing control design and STA. Perform chip bring-up, validation, and debugging. Design, integrate, and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow. Coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, Cadence Virtuoso, Design Compiler, Integrator, and programming languages Verilog and SystemVerilog. Work on enhancing the functionality of the grp_holdip. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Collaborate with sensor digital and analog engineers for system design, integration, and validation. Work with algorithm engineers for module level design, including hardware C model implementation, microarchitecture design, RTL design, and hardware/software co-simulation. Coordinate with algorithm and application engineers for image tuning and qualification. Conduct silicon validation, debugging, and tuning. Job Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or related fields with coursework in Digital System Design, MOS VLSI Circuit Design, Asynchronous VLSI Design, Computer Systems Architecture, and Network Processor Design and Programming. Required Skills
Digital simulator and waveform viewer. RTL Design/coding, Verification, Simulation, and debugging. Circuit design and simulation in CMOS and/or VLSI. Verification language: SystemVerilog, Verilog. Understanding of CPU microarchitecture (out-of-order execution, register renaming, reservation stations, processor pipelines). Knowledge of computer architecture subsystems, cache hierarchy, and data hazards. Proficiency in Python, Assembly, Shell, and Perl scripting. Experience with Linux and source control systems. Annual base salary in California, US is expected to be between $151,091 and $155,000. Actual pay depends on skills, experience, and market conditions. Additional Details
Seniority level: Entry level Employment type: Full-time Job function: Engineering and Information Technology Industry: Semiconductor Manufacturing This job posting is active. No indication of expiration found.
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SoC Design Engineer
role at
OMNIVISION . Get AI-powered advice on this job and more exclusive features. Responsibilities
Be responsible for digital design of image sensor, SoC integration, and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure, and DFT. Conduct image sensor array/analog related timing control design and STA. Perform chip bring-up, validation, and debugging. Design, integrate, and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow. Coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, Cadence Virtuoso, Design Compiler, Integrator, and programming languages Verilog and SystemVerilog. Work on enhancing the functionality of the grp_holdip. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Collaborate with sensor digital and analog engineers for system design, integration, and validation. Work with algorithm engineers for module level design, including hardware C model implementation, microarchitecture design, RTL design, and hardware/software co-simulation. Coordinate with algorithm and application engineers for image tuning and qualification. Conduct silicon validation, debugging, and tuning. Job Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or related fields with coursework in Digital System Design, MOS VLSI Circuit Design, Asynchronous VLSI Design, Computer Systems Architecture, and Network Processor Design and Programming. Required Skills
Digital simulator and waveform viewer. RTL Design/coding, Verification, Simulation, and debugging. Circuit design and simulation in CMOS and/or VLSI. Verification language: SystemVerilog, Verilog. Understanding of CPU microarchitecture (out-of-order execution, register renaming, reservation stations, processor pipelines). Knowledge of computer architecture subsystems, cache hierarchy, and data hazards. Proficiency in Python, Assembly, Shell, and Perl scripting. Experience with Linux and source control systems. Annual base salary in California, US is expected to be between $151,091 and $155,000. Actual pay depends on skills, experience, and market conditions. Additional Details
Seniority level: Entry level Employment type: Full-time Job function: Engineering and Information Technology Industry: Semiconductor Manufacturing This job posting is active. No indication of expiration found.
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