Senior Digital Verification Engineer – HDL/Verilog, UVM, SVA (Onsite)

A leading defense contractor is looking for a Staff Digital Verification Engineer in Jessup, Maryland. The role involves developing full-custom digital circuits and requires proficiency in HDL (VHDL/Verilog) and HVL (SystemVerilog). Candidates are expected to have significant experience in verification methodologies and strong communication skills. Benefits include comprehensive healthcare and education assistance, along with a competitive salary range of $185,900.00 to $278,900.00. #J-18808-Ljbffr