Senior Design Verification Lead - SoC & IP Strategy

A leading semiconductor company is seeking a Senior Design Verification Engineer in Santa Clara, California. This role involves designing and implementing verification strategies for next-generation chassis IPs, collaborating closely with various teams throughout the product development cycle, and mentoring junior engineers. The ideal candidate will have extensive experience in design verification and a deep understanding of interconnect protocols and memory architecture, along with strong coding skills in System Verilog, C/C++, and Python. Competitive benefits and a strong compensation package are offered. #J-18808-Ljbffr