Senior ASIC Design Engineer

Asic Design Engineer • San Francisco, CA, US

Responsibilities

Define and bring up FPGA platforms for pre-silicon validation and software development

Map ASIC RTL to FPGA while minimizing code base differences

Create and execute test plans for validating SoC functionality and performance

Resolve challenging system level issues that span multiple disciplines

Design logic starting from specification or high level feature description

Requirements

Minimum of 5 years of relevant experience.

Scripting or programming experience in Python or C/C++

Ability to write and analyze the completeness of constraints

Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters

Strong analytical and debugging skills

BS in Electrical Engineering or equivalent required, MS preferred

Nice to Have

Familiarity with Xilinx FPGA’s and Vivado tool chain

Experience with validating and debugging low-power wireless systems

Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)

Knowledge of wireless protocols (e.g. Bluetooth Low Energy)

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