Expedite Technology Solutions LLC
US_East | Network Design Engineer_L3
Expedite Technology Solutions LLC, Chicago, Illinois, United States, 60290
Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential
TMR ID: # Z8TSS2 Role: Design Verification Engineer Work location: Santa Clara, CA. Background and Meet and Greet: MANDATORY
Job Description: Design Verification Engineer
Key Responsabilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
Mandatory skills and skill proficiencies required for this position: • Synopsys/Cadence EDA Verifications tools (Preference: 5) • SystemVerilog/UVM (Preference: 5)
The following details must accompany your submission:
First Name, Middle name, and Last Name: City and State: Open to Relocate? Rate: Availability: Phone #: Mobile #: Email address: Visa type: Visa Expiration Date: Hiring Status:
TMR ID: # Z8TSS2 Role: Design Verification Engineer Work location: Santa Clara, CA. Background and Meet and Greet: MANDATORY
Job Description: Design Verification Engineer
Key Responsabilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
Mandatory skills and skill proficiencies required for this position: • Synopsys/Cadence EDA Verifications tools (Preference: 5) • SystemVerilog/UVM (Preference: 5)
The following details must accompany your submission:
First Name, Middle name, and Last Name: City and State: Open to Relocate? Rate: Availability: Phone #: Mobile #: Email address: Visa type: Visa Expiration Date: Hiring Status: