Datum Technologies Group
Design Verification Engineer
Datum Technologies Group, Santa Clara, California, United States, 95050
Design Verification Engineer
Role: Design Verification Engineer Location: Santa Clara, CA Job Description: We are seeking a highly skilled Design Verification Engineer to join our team in Santa Clara, CA. The ideal candidate will have hands-on experience in creating verification environments and working with SystemVerilog/UVM for IPs and SoCs that include embedded CPUs and analog mixed-signal interfaces.
Role: Design Verification Engineer Location: Santa Clara, CA Job Description: We are seeking a highly skilled Design Verification Engineer to join our team in Santa Clara, CA. The ideal candidate will have hands-on experience in creating verification environments and working with SystemVerilog/UVM for IPs and SoCs that include embedded CPUs and analog mixed-signal interfaces.